1. Field of the Invention
The present invention relates generally to the field of printed circuit board. More particularly, the present invention relates to a footprint on PCB for leadframe-based packages, which is capable of improving the yield when surface mounting leadframe-based packages to the PCB.
2. Description of the Prior Art
There are various leadframe-based surface mount components, such as quad flat no-lead (QFN) package, advanced QFN (aQFN) package, low-profile quad flat package (LQFP) or the like. A package can be attached to a printed circuit board (PCB) by, for example, soldering it to the PCB. The attachment of the packages (i.e. packaged integrated circuit) to PCBs produces printed circuit board assemblies (PCBAs), which can be used as motherboards in computers, portable devices such as mobile phone, tablets, notebooks, etc.
To solder the package to the PCB, solder paste can be applied to the surface of the PCB at appropriate regions. The solder paste can be applied to the PCB surface by stencil printing method. After the application of solder paste, the package can be positioned on the PCB, and the assembly can be placed into an oven and heated. The heating cause the solder to melt, leading to wetting and wicking. A solder mask can also be applied on the PCB to control the solder paste during heating. The solder mask defines openings on the outer layer of the PCB and exposes the copper circuit pattern such as input/output (I/O) pads, ground pads, power pads, and/or thermal pads of the PCB. The solder mask is placed on the PCB, and solder paste is applied to areas of the PCB to which the package is to be attached that are not protected by a solder mask.
FIG. 1 shows a conventional footprint 100 of a portion of a PCB 110 to which a package, such as a QFN, may be attached. The footprint 100 includes a single, monolithic pad 210 within a central region 101 (indicated by the dotted line) and an array of I/O pads 220 and 222 disposed within a peripheral region 102 surrounding the central region 101. The pad 210 has a surface area that is equal to or slightly larger than a ground pad of the package (not shown). Typically, the contour of the pad 210 is substantially the same as that of the ground pad. Vias 212 are located within the central region 101, which may conduct heat and/or signal between the pad 210 and at least one interior layer of the PCB 110 and the opposite surface of the PCB 110. The ground pad on the bottom side of the package may be soldered to the pad 210 to provide thermal conductivity and a mechanical connection and can also provide an electrical connection. The attachment of the package to the footprint may be carried out by surface mount technology (SMT).
The soldering quality is critical to assembly of packages. To assess soldering quality, visual inspection or automatic optical inspection machine is typically employed. However, the yield of the conventional SMT for attaching leadframe-based packages, such as QFN, aQFN, LQFP or the like, to the footprint as described above is not satisfactory. During visual inspection, defects such as empty solder and cold solder joint are often observed at the inner soldering sites such as solder pads 222 that are located in proximity to the pad 210. It is believed that such defects (empty solder and cold solder joint) are due to the relatively large size of the pad 210 that dissipates heat faster. Therefore, there is a need in this industry to provide a solution to solve the defective soldering problems when attaching a leadframe-based package to PCB.